Field
This disclosure relates generally to semiconductor contacts, and more specifically, to contacts for a non-volatile memory.
Related Art
Non-volatile memories (NVMs) continue to grow in importance. It has become common for at least small amounts of NVM to be present on an integrated circuit. Also stand alone NVMs continue to be important. In non-volatile memories, it is common for adjacent memory cells to share adjacent source/drain regions in which case a contact to the common source/drain region is between gate stacks of the adjacent memory cells. The gate stacks are close together to save space. The placement of the contact is thus critical. Due to misalignment, the contact can be very close to the gate stack so that only a thin dielectric remains between the contact and the gate stack. With the relatively high voltages used in programming and erasing NVM cells, the thin dielectric resulting from a misaligned contact may result in a voltage breakdown of the thin dielectric, shorting the gate stack to the contact. Thus, the gate stacks need to be sufficiently far apart to prevent the contact, in a misalignment situation, from shorting to the closest gate stack which is most likely to occur during program or erase when higher voltages are applied.
Thus there is a need for improving the misalignment tolerance for a contact being formed between gate stacks of an NVM.